 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HM621664HBI Series 65536-word x 16-bit High Speed CMOS Static RAM ADE-203-786 A(Z) Rev. 1.0 May. 19, 1997 Description The HM621664HBI is an asynchronous high speed static RAM organized as 64-kword x 16-bit. It realize high speed access time (20 ns) with employing 0.8 m CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM621664HBI is packaged in 400-mil 44-pin SOJ for high density surface mounting. Features * Single 5 V supply: 5 V 10% * Access time: 20 ns (max) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible All inputs and outputs * 400-mil 44-pin SOJ package * Center VCC and VSS type pinout * Operating temperature range: -40 to +85C Ordering Information Type No. HM621664HBLJPI-20 Access time 20 ns Package 400-mil 44-pin plastic SOJ (CP-44D) HM621664HBI Series Pin Arrangement HM621664HBLJPI Series A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC (Top View) Pin Description Pin name A0 to A15 I/O1 to I/O16 CS OE WE UB LB VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Upper byte select Lower byte select Power supply Ground No connection 2 HM621664HBI Series Block Diagram (LSB) A3 A2 A1 A0 A7 A6 A5 A4 VCC Row decoder Memory matrix 256 rows x 256 columns x 16 bit (1,048,576 bits) VSS (MSB) CS I/O1 . . . I/O8 I/O9 . . . I/O16 WE CS LB UB Column I/O Input data control Column decoder CS (LSB) A12 A11 A10 A15 A14 A13 A9 A8 (MSB) OE CS Function Table CS H L L L L L L L L L Note: OE x H L L L L x x x x WE x H H H H H L L L L x: H or L LB x x L L H H L L H H UB x x L H L H L H L H Mode Standby Output disable Read VCC current I SB , I SB1 I CC I CC I/O1-I/O8 High-Z High-Z Output Output High-Z High-Z Input Input High-Z High-Z I/O9-I/O16 High-Z High-Z Output High-Z Output High-Z Input High-Z Input High-Z Ref. cycle -- -- Read cycle Read cycle Read cycle -- Write cycle Write cycle Write cycle -- Lower byte read I CC Upper byte read I CC -- Write I CC I CC Lower byte write I CC Upper byte write I CC -- I CC 3 HM621664HBI Series Absolute Maximum Ratings Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5* to V CC + 0.5 1.0* /1.5* 2 3 1 Unit V V W C C C -40 to +85 -55 to +125 -40 to +85 Notes: 1. VT (min) = -2.5 V for pulse width (under shoot) 10 ns 2. At still air condition 3. At air flow 1.0 m/s Recommended DC Operating Conditions (Ta = -40 to +85C) Parameter Supply voltage Symbol VCC* VSS * Input voltage VIH VIL 2 3 Min 4.5 0 2.4 -0.5* 1 Typ 5.0 0 -- -- Max 5.5 0 VCC + 0.5 0.6 Unit V V V V Notes: 1. -2.0 V for pulse width (under shoot) 10 ns 2. The supply voltage with all VCC pins must be on the same level. 3. The supply voltage with all VSS pins must be on the same level. 4 HM621664HBI Series DC Characteristics (Ta = -40 to +85C, VCC = 5 V 10%, VSS = 0 V) Parameter Input leakage current Output leakage current Operating power supply current Standby power supply current Symbol Min |ILI| |ILO | I CC I SB I SB1 -- -- -- -- -- Typ*1 -- -- 130 45 -- Max 2.0 2.0 150 80 0.5 Unit Test conditions A A mA mA mA Vin = VSS to V CC Vin = VSS to V CC CS = VIL, Iout = 0 mA Other inputs = VIH/VIL CS = VIH, Other inputs = VIH/VIL VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V I OL = 8 mA I OH = -4 mA Output voltage VOL VOH -- 2.4 -- -- 0.4 -- V V Note: 1. Typical values are at VCC = 5.0 V, Ta = +25C and specified loading. Capacitance (Ta = 25C, f = 1.0 MHz) Parameter Input capacitance* 1 1 Symbol Cin CI/O Min -- -- Typ -- -- Max 6 8 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Input/output capacitance* Note: 1. This parameter is sampled and not 100% tested. 5 HM621664HBI Series AC Characteristics (Ta = -40 to +85C, VCC = 5 V 10%, unless otherwise noted.) Test Conditions * * * * Input pulse levels: 0 V to 3.5 V Input rise and fall time: 3.0 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope & jig) 5V 5V 480 Dout 255 30 pF* Dout 255 480 5 pF* Output load (A) Output load (B) (for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ, tLBHZ, tUBHZ, tWHZ, and tOW) Read Cycle HM621664HB -20 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Byte select to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Byte select to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Byte deselect to output in high-Z Symbol t RC t AA t ACS t OE t LB, t UB t OH t CLZ t OLZ t LBLZ, t UBLZ t CHZ t OHZ t LBHZ, t UBHZ Min 20 -- -- -- -- 5 3 1 1 -- -- -- Max -- 20 20 10 10 -- -- -- -- 7 7 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 Notes 6 HM621664HBI Series Write Cycle HM621664HB -20 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Byte select to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Output disable to output in high-Z Write enable to output in high-Z Symbol t WC t AW t CW t WP t LBW, t UBW t AS t WR t DW t DH t OW t OHZ t WHZ Min 20 15 12 12 12 0 2 10 1 3 -- -- Max -- -- -- -- -- -- -- -- -- -- 7 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 8 7 9, 10 5 6 Notes Notes: 1. Transition is measured 200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 3. WE and/or CS must be high during address transition time. 4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. t AS is measured from the latest address transition to the latest of CS, WE, LB or UB going low. 6. t WR is measured from the earliest of CS, WE, LB or UB going high to the first address transition. 7. A write occurs during the overlap of low CS, low WE and low LB or low UB. 8. t CW is measured from the later of CS going low to the end of write. 9. t LBW is measured from the later of LB going low to the end of write. 10. t UBW is measured from the later of UB going low to the end of write. 7 HM621664HBI Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) tRC Address tAA tACS CS tOE OE tLB LB tLBHZ 1 * tOHZ *1 tCHZ *1 Valid address tUB UB tLBLZ *1 Dout (Lower byte) High Impedance *4 tUBLZ *1 tOLZ *1 tCLZ *1 High Impedance *4 Valid data tUBHZ1 * *4 tOH Dout (Upper byte) Valid data *4 8 HM621664HBI Series Read Timing Waveform (2) (WE = VIH, LB = VIL , UB, = VIL) tRC Address Valid address tAA tACS tOH tCHZ*1 CS tOE OE tOLZ*1 tCLZ *1 Dout (Lower/Upper byte) High Impedance *4 Valid data *4 tOHZ*1 9 HM621664HBI Series Write Timing Waveform (1) (LB, UB Controlled) tWC Address tAW tAS tWP WE*3 tCW CS*3 Valid address tWR OE tLBW LB tUBW UB tWHZ tOHZ High impedance tOLZ tOW Dout (Lower byte) Dout (Upper byte) High impedance tDW tDH Valid data tDW tDH Valid data Din (Lower byte) Din (Upper byte) 10 HM621664HBI Series Write Timing Waveform (2) (WE Controlled) tWC Address tAW tAS WE*3 tCW CS*3 tWP Valid address tWR OE tLBW LB, UB tWHZ tOHZ Dout (Lower/Upper byte) High impedance *2 tOLZ tOW tUBW tDW tDH Valid data Din (Lower/Upper byte) 11 HM621664HBI Series Write Timing Waveform (3) (CS Controlled) tWC Address Valid address tAW tAS tWP tWR WE *3 tCW CS *3 OE tLBW LB, UB tWHZ tOHZ Dout (Lower/Upper byte) High impedance * *2 4 tUBW tOLZ tOW tDW tDH Valid data Din (Lower/Upper byte) 12 HM621664HBI Series Low VCC Data Retention Characteristics (Ta = -40 to +85C) Parameter VCC for data retention Symbol VDR Min 2.0 Typ*1 Max -- -- Unit V Test conditions VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V VCC = 3 V VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V See retention waveform Data retention current I CCDR -- 2 200 A Chip deselect to data retention time Operation recovery time Note: t CDR tR 0 50 -- -- -- -- ns ms 1. Typical values are at VCC = 3.0 V, Ta = 25C, and not guaranteed. Low V CC Data Retention Timing Waveform tCDR VCC 4.5 V Data retention mode tR 2.4 V VDR CS 0V CS VCC - 0.2 V 13 HM621664HBI Series Package Dimensions HM621664HBLJPI Series (CP-44D) Unit: mm 28.33 28.90 Max 44 23 10.16 0.13 0.74 1.30 Max 3.50 0.26 1 22 11.18 0.13 0.80 +0.25 -0.17 0.43 0.10 0.41 0.08 1.27 9.40 0.25 Hitachi Code JEDEC Code EIAJ Code Weight CP-44D MO-061-AE -- 1.8 g 0.10 14 2.65 0.12 HM621664HBI Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 15 HM621664HBI Series Revision Record Rev. 1.0 Date May. 19, 1997 Contents of Modification Initial issue Drawn by Approved by 16 |
Price & Availability of HM621664HBISERIES
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |